Introduction¶
SymbiFlow is a Open Source Verilog-to-Bitstream FPGA synthesis flow, currently targeting Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs. Think of it as the GCC of FPGAs.
The project aim is to design tools that are highly extendable and multiplatform.
EDA Tooling Ecosystem¶
For both ASIC- and FPGA-oriented EDA tooling, there are three major areas that the workflow needs to cover: hardware description, frontend and backend.
Hardware description languages are generally open, with both established HDLs such as Verilog and VHDL and emerging software-inspired paradigms like Chisel, SpinalHDL or Migen. The major problem lies however in the front- and backend, where previously there was no established standard, vendor-neutral tooling that would cover all the necessary components for an end-to-end flow.
This pertains both to ASIC and FPGA workflows, although SymbiFlow focuses on the latter (some parts of SymbiFlow will also be useful in the former).
Project structure¶
To achieve SymbiFlow’s goal of a complete FOSS FPGA toolchain, a number of tools and projects are necessary to provide all the needed components of an end-to-end flow. Thus, SymbiFlow serves as an umbrella project for several activities, the central of which pertains to the creation of so-called FPGA “architecture definitions”, i.e. documentation of how specific FPGAs work internally. More information can be found in the Symbiflow Architecture Definitions project.
Those definitions and serve as input to backend tools like nextpnr and Verilog to Routing, and frontend tools like Yosys. They are created within separate collaborating projects targeting different FPGAs - Project X-Ray for Xilinx 7-Series, Project IceStorm for Lattice iCE40 and Project Trellis for Lattice ECP5 FPGAs.
Current status of bitstream documentation¶
Projects |
IceStorm |
X-Ray |
Trellis |
|---|---|---|---|
Basic Tiles |
|||
Logic |
Yes |
Yes |
Yes |
Block RAM |
Yes |
Partial |
N/A |
Advanced Tiles |
|||
DSP |
Yes |
No |
Yes |
Hard Blocks |
Yes |
No |
Yes |
Clock Tiles |
Yes |
Partial |
Yes |
IO Tiles |
Yes |
Partial |
Yes |
Routing |
|||
Logic |
Yes |
Yes |
Yes |
Clock |
Yes |
Partial |
Yes |