Fuzzers¶
Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion. This is how the contents of the database are generated.
The general idea behind fuzzers is to pick some element in the device (say a block RAM or IOB) to target. If you picked the IOB (no one is working on that yet), you’d write a design that is implemented in a specific IOB. Then you’d create a program that creates variations of the design (called specimens) that vary the design parameters, for example, changing the configuration of a single pin.
A lot of this program is TCL that runs inside Vivado to change the design parameters, because it is a bit faster to load in one Verilog model and use TCL to replicate it with varying inputs instead of having different models and loading them individually.
By looking at all the resulting specimens, you can correlate which bits in which frame correspond to a particular choice in the design.
Looking at the implemented design in Vivado with “Show Routing Resources” turned on is quite helpful in understanding what all choices exist.
Configurable Logic Blocks (CLB)¶
Block RAM (BRAM)¶
Input / Output (IOB)¶
Clocking (CMT, PLL, BUFG, etc)¶
- HCLK_IOI interconnect fuzzer
- BUFG interconnect fuzzer
- BUFG interconnect fuzzer
- HCLK_CMT interconnect fuzzer
- HCLK_IOI interconnect fuzzer
- Fuzzer for INT PIPs driving the CLK wires
- Fuzzer for PIPs in HCLK titles
- MMCM
- Clock Management Tile (CMT) - Phase Lock Loop (PLL) Fuzzer
- Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
Programmable Interconnect Points (PIPs)¶
- HCLK_IOI interconnect fuzzer
- BUFG interconnect fuzzer
- BUFG interconnect fuzzer
- Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
- HCLK_CMT interconnect fuzzer
- HCLK_IOI interconnect fuzzer
- Fuzzer for bidirectional INT PIPs
- Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs
- Fuzzer for INT PIPs driving the CLK wires
- Fuzzer for INT PIPs driving the CTRL wires
- Fuzzer for the FAN_ALT.*GFAN PIPs and BYP_ALT.*GFAN PIPs
- Fuzzer for INT PIPs driving the GFAN wires with GND
- Fuzzer for PIPs in HCLK titles
- Fuzzer for INT LOGIC_OUTS -> IMUX PIPs
- Fuzzer for the remaining INT PIPs
- Generic fuzzer for INT PIPs
Hard Block Fuzzers¶
Grid and Wire¶
All Fuzzers¶
- HCLK_IOI interconnect fuzzer
- BRAM Configuration
- BRAM Data
- cfg fuzzer
- clb-ffconfig Fuzzer
- clb-ffsrcemux Fuzzer
- clb-lutinit Fuzzer
- clb-n5ffmux Fuzzer
- clb-ncy0 Fuzzer
- clb-ndi1mux Fuzzer
- clb-nffmux Fuzzer
- clb-noutmux Fuzzer
- clb-precyinit Fuzzer
- clb-ram Fuzzer
- BUFG interconnect fuzzer
- BUFG interconnect fuzzer
- MMCM
- Clock Management Tile (CMT) - Phase Lock Loop (PLL) Fuzzer
- Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
- HCLK_CMT interconnect fuzzer
- HCLK_IOI interconnect fuzzer
- IOB Fuzzer
- XADC Fuzzer
- Fuzzer for bidirectional INT PIPs
- Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs
- Fuzzer for INT PIPs driving the CLK wires
- Fuzzer for INT PIPs driving the CTRL wires
- Fuzzer for the FAN_ALT.*GFAN PIPs and BYP_ALT.*GFAN PIPs
- Fuzzer for INT PIPs driving the GFAN wires with GND
- Fuzzer for PIPs in HCLK titles
- Fuzzer for INT LOGIC_OUTS -> IMUX PIPs
- Fuzzer for the remaining INT PIPs
- Generic fuzzer for INT PIPs
- PS7 verilog cell definition extractor
- Tilegrid Fuzzer