SymbiFlow

Table Of Contents

SymbiFlow documentation

• Introduction
  • EDA Tooling Ecosystem
  • Project structure
  • Current status of bitstream documentation
• Toolchain description
  • FPGA Design Flow
    • Synthesis
    • Place & Route
    • Bitstream translation
  • Yosys
    • Short description
    • Usage in Toolchain
    • Output analysis
    • More information
  • VPR
    • Basic flow
    • Command-line Options
    • Graphics
    • Timing Constraints
    • SDC Commands
    • File Formats
    • Debugging Aids
• Welcome to Project X-Ray
  • Overview
  • Configuration
    • Addressing
    • Loading sequence
    • Other
  • Bitstream format
    • Xilinx
  • Interconnect PIPs
    • Fake PIPs
    • Regular PIPs
    • VCC Drivers
    • Bidirectional PIPs
  • Distributed RAMs (DRAM / SLICEM)
    • Functions
    • Configuration
  • Glossary
  • References
    • Xilinx documents one should be familiar with:
    • Other documentation that might be of use:
  • Contributor Covenant Code of Conduct
    • Our Pledge
    • Our Standards
    • Our Responsibilities
    • Scope
    • Enforcement
    • Attribution
  • Guide to updating the Project X-Ray docs
    • 1. Make your updates
    • 2. Test your updates
    • 3. Send a pull request
  • Project X-Ray
  • Quickstart Guide
    • Step 1:
    • Step 2:
    • Step 3:
    • Step 4:
    • Step 5:
    • Step 6:
    • Step 7:
    • Step 8:
    • Step 9:
  • C++ Development
  • Process
    • Parts
  • Database
  • Current Focus
    • TODO List
  • Contributing
    • Sending
    • License
    • Code of Conduct
    • Sign your work
    • Contributing to the docs
  • Contributing to Project X-Ray
    • Sending
    • License
    • Code of Conduct
    • Sign your work
    • Contributing to the docs
  • Fuzzers
    • Configurable Logic Blocks (CLB)
    • Block RAM (BRAM)
    • Input / Output (IOB)
    • Clocking (CMT, PLL, BUFG, etc)
    • Programmable Interconnect Points (PIPs)
    • Hard Block Fuzzers
    • Grid and Wire
    • All Fuzzers
  • Minitests
    • CLB_BUSED Minitest
    • CLB_MUXF8 Minitest
    • FIXEDPNR Minitest
    • Minitests for ISERDES+IDELAY
    • ISERDES minitest for SDR and DDR
    • LiteX minitest
    • LiteX Litex BaseSoC + LiteDRAM minitest
    • Minitest for OSERDES
    • FASM Proof of Concept using Vivado Partial Reconfig flow
    • PICORV32-v Minitest
    • PICORV32-y Minitest
    • PLLE2_ADV minitest
    • ROI_HARNESS Minitest
    • Minitests for SRLs
    • Timing minitest
    • Zynq7 EMIO minitest
    • Building & loading
  • Tools
  • .db Files
    • Introduction
    • Segment bit positions
    • segbits_*.db
    • ppips_*.db
    • mask_*.db
    • .bits example
  • .json Files
    • Introduction
    • tilegrid.json
    • tileconn.json
• Welcome to Project Trellis
  • Overview
  • Tiles
    • Logic Tiles
    • Common Interconnect Blocks (CIBs)
    • IO Tiles
    • Global Clock Tiles
    • Embedded Block RAM (EBR)
    • DSP Tiles
    • System and Config Tiles
  • General Routing
  • Global Routing
    • Mid Muxes
    • Centre Muxes
    • Spine Tiles
    • TAP_DRIVE Tiles
    • Non-Clock Global Usage
  • Bitstream format
    • Basic Structure
    • Control Commands
    • Configuration Data
    • Compression Algorithm
    • Partial Bitstreams
    • Device-Specific Information
  • Glossary
  • Database Development Overview
    • NCL Files
    • Fuzzers
  • libtrellis Overview
    • Bitstream
    • Chip
    • CRAM
    • Tile
    • TileConfig
    • TileBitDatabase
    • RoutingGraph
    • DedupChipdb
    • ChipConfig
  • Textual Configuration Format
    • Overview
    • Non-Tile Configuration
    • Tile Configuration
    • Conversion
  • DSP Support
    • Structure
    • Multiplier
    • Adder
    • Macs
• FPGA ASM (FASM) Specification
  • Introduction
  • File Syntax description
    • Lines
    • Annotations
    • Formal syntax specification of a line of a FASM file
    • Canonicalization
  • Meaning of a FASM line
    • Feature
    • FeatureAddress and FeatureValue

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Introduction