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Table Of Contents
Introduction
Toolchain description
FPGA Design Flow
Yosys
VPR
Basic flow
Command-line Options
Graphics
Timing Constraints
SDC Commands
File Formats
Debugging Aids
Welcome to Project X-Ray
Overview
Configuration
Bitstream format
Interconnect
PIPs
Distributed RAMs (DRAM / SLICEM)
Glossary
References
Contributor Covenant Code of Conduct
Guide to updating the Project X-Ray docs
Project X-Ray
Quickstart Guide
C++ Development
Process
Database
Current Focus
Contributing
Contributing to Project X-Ray
Fuzzers
clb-ffconfig Fuzzer
clb-ffsrcemux Fuzzer
clb-lutinit Fuzzer
clb-n5ffmux Fuzzer
clb-ncy0 Fuzzer
clb-ndi1mux Fuzzer
clb-nffmux Fuzzer
clb-noutmux Fuzzer
clb-precyinit Fuzzer
clb-ram Fuzzer
BRAM Configuration
BRAM Data
IOB Fuzzer
HCLK_IOI interconnect fuzzer
BUFG interconnect fuzzer
BUFG interconnect fuzzer
HCLK_CMT interconnect fuzzer
HCLK_IOI interconnect fuzzer
Fuzzer for INT PIPs driving the CLK wires
Fuzzer for PIPs in HCLK titles
MMCM
Clock Management Tile (CMT) - Phase Lock Loop (PLL) Fuzzer
Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
HCLK_IOI interconnect fuzzer
BUFG interconnect fuzzer
BUFG interconnect fuzzer
Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
HCLK_CMT interconnect fuzzer
HCLK_IOI interconnect fuzzer
Fuzzer for bidirectional INT PIPs
Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs
Fuzzer for INT PIPs driving the CLK wires
Fuzzer for INT PIPs driving the CTRL wires
Fuzzer for the FAN_ALT.*GFAN PIPs and BYP_ALT.*GFAN PIPs
Fuzzer for INT PIPs driving the GFAN wires with GND
Fuzzer for PIPs in HCLK titles
Fuzzer for INT LOGIC_OUTS -> IMUX PIPs
Fuzzer for the remaining INT PIPs
Generic fuzzer for INT PIPs
XADC Fuzzer
Tilegrid Fuzzer
HCLK_IOI interconnect fuzzer
BRAM Configuration
BRAM Data
cfg fuzzer
clb-ffconfig Fuzzer
clb-ffsrcemux Fuzzer
clb-lutinit Fuzzer
clb-n5ffmux Fuzzer
clb-ncy0 Fuzzer
clb-ndi1mux Fuzzer
clb-nffmux Fuzzer
clb-noutmux Fuzzer
clb-precyinit Fuzzer
clb-ram Fuzzer
BUFG interconnect fuzzer
BUFG interconnect fuzzer
MMCM
Clock Management Tile (CMT) - Phase Lock Loop (PLL) Fuzzer
Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
HCLK_CMT interconnect fuzzer
HCLK_IOI interconnect fuzzer
IOB Fuzzer
XADC Fuzzer
Fuzzer for bidirectional INT PIPs
Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs
Fuzzer for INT PIPs driving the CLK wires
Fuzzer for INT PIPs driving the CTRL wires
Fuzzer for the FAN_ALT.*GFAN PIPs and BYP_ALT.*GFAN PIPs
Fuzzer for INT PIPs driving the GFAN wires with GND
Fuzzer for PIPs in HCLK titles
Fuzzer for INT LOGIC_OUTS -> IMUX PIPs
Fuzzer for the remaining INT PIPs
Generic fuzzer for INT PIPs
PS7 verilog cell definition extractor
Tilegrid Fuzzer
Minitests
CLB_BUSED Minitest
CLB_MUXF8 Minitest
FIXEDPNR Minitest
Minitests for ISERDES+IDELAY
ISERDES minitest for SDR and DDR
LiteX minitest
LiteX Litex BaseSoC + LiteDRAM minitest
Minitest for OSERDES
FASM Proof of Concept using Vivado Partial Reconfig flow
PICORV32-v Minitest
PICORV32-y Minitest
PLLE2_ADV minitest
ROI_HARNESS Minitest
Minitests for SRLs
Timing minitest
Zynq7 EMIO minitest
Building & loading
Tools
.db Files
.json Files
Welcome to Project Trellis
Overview
Tiles
General Routing
Global Routing
Bitstream format
Glossary
Database Development Overview
libtrellis Overview
Textual Configuration Format
DSP Support
FPGA ASM (FASM) Specification
SymbiFlow
Table Of Contents
Introduction
Toolchain description
FPGA Design Flow
Yosys
VPR
Basic flow
Command-line Options
Graphics
Timing Constraints
SDC Commands
File Formats
Debugging Aids
Welcome to Project X-Ray
Overview
Configuration
Bitstream format
Interconnect
PIPs
Distributed RAMs (DRAM / SLICEM)
Glossary
References
Contributor Covenant Code of Conduct
Guide to updating the Project X-Ray docs
Project X-Ray
Quickstart Guide
C++ Development
Process
Database
Current Focus
Contributing
Contributing to Project X-Ray
Fuzzers
clb-ffconfig Fuzzer
clb-ffsrcemux Fuzzer
clb-lutinit Fuzzer
clb-n5ffmux Fuzzer
clb-ncy0 Fuzzer
clb-ndi1mux Fuzzer
clb-nffmux Fuzzer
clb-noutmux Fuzzer
clb-precyinit Fuzzer
clb-ram Fuzzer
BRAM Configuration
BRAM Data
IOB Fuzzer
HCLK_IOI interconnect fuzzer
BUFG interconnect fuzzer
BUFG interconnect fuzzer
HCLK_CMT interconnect fuzzer
HCLK_IOI interconnect fuzzer
Fuzzer for INT PIPs driving the CLK wires
Fuzzer for PIPs in HCLK titles
MMCM
Clock Management Tile (CMT) - Phase Lock Loop (PLL) Fuzzer
Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
HCLK_IOI interconnect fuzzer
BUFG interconnect fuzzer
BUFG interconnect fuzzer
Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
HCLK_CMT interconnect fuzzer
HCLK_IOI interconnect fuzzer
Fuzzer for bidirectional INT PIPs
Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs
Fuzzer for INT PIPs driving the CLK wires
Fuzzer for INT PIPs driving the CTRL wires
Fuzzer for the FAN_ALT.*GFAN PIPs and BYP_ALT.*GFAN PIPs
Fuzzer for INT PIPs driving the GFAN wires with GND
Fuzzer for PIPs in HCLK titles
Fuzzer for INT LOGIC_OUTS -> IMUX PIPs
Fuzzer for the remaining INT PIPs
Generic fuzzer for INT PIPs
XADC Fuzzer
Tilegrid Fuzzer
HCLK_IOI interconnect fuzzer
BRAM Configuration
BRAM Data
cfg fuzzer
clb-ffconfig Fuzzer
clb-ffsrcemux Fuzzer
clb-lutinit Fuzzer
clb-n5ffmux Fuzzer
clb-ncy0 Fuzzer
clb-ndi1mux Fuzzer
clb-nffmux Fuzzer
clb-noutmux Fuzzer
clb-precyinit Fuzzer
clb-ram Fuzzer
BUFG interconnect fuzzer
BUFG interconnect fuzzer
MMCM
Clock Management Tile (CMT) - Phase Lock Loop (PLL) Fuzzer
Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
HCLK_CMT interconnect fuzzer
HCLK_IOI interconnect fuzzer
IOB Fuzzer
XADC Fuzzer
Fuzzer for bidirectional INT PIPs
Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs
Fuzzer for INT PIPs driving the CLK wires
Fuzzer for INT PIPs driving the CTRL wires
Fuzzer for the FAN_ALT.*GFAN PIPs and BYP_ALT.*GFAN PIPs
Fuzzer for INT PIPs driving the GFAN wires with GND
Fuzzer for PIPs in HCLK titles
Fuzzer for INT LOGIC_OUTS -> IMUX PIPs
Fuzzer for the remaining INT PIPs
Generic fuzzer for INT PIPs
PS7 verilog cell definition extractor
Tilegrid Fuzzer
Minitests
CLB_BUSED Minitest
CLB_MUXF8 Minitest
FIXEDPNR Minitest
Minitests for ISERDES+IDELAY
ISERDES minitest for SDR and DDR
LiteX minitest
LiteX Litex BaseSoC + LiteDRAM minitest
Minitest for OSERDES
FASM Proof of Concept using Vivado Partial Reconfig flow
PICORV32-v Minitest
PICORV32-y Minitest
PLLE2_ADV minitest
ROI_HARNESS Minitest
Minitests for SRLs
Timing minitest
Zynq7 EMIO minitest
Building & loading
Tools
.db Files
.json Files
Welcome to Project Trellis
Overview
Tiles
General Routing
Global Routing
Bitstream format
Glossary
Database Development Overview
libtrellis Overview
Textual Configuration Format
DSP Support
FPGA ASM (FASM) Specification
Index
Symbols
|
A
|
B
|
C
|
D
|
F
|
G
|
H
|
I
|
L
|
M
|
N
|
O
|
P
|
Q
|
R
|
S
|
T
|
V
|
W
Symbols
#(comment),\\(linecontinued),*(wildcard),{}(stringescape)
SDC Command
$VTR_ROOT
--absorb_buffer_luts {on | off}
vpr command line option
--acc_fac <float>
vpr command line option
--activity_file <file>
vpr command line option
--allow_unrelated_clustering {on | off | auto}
vpr command line option
--alpha_clustering <float>
vpr command line option
--alpha_t <float>
vpr command line option
--analysis
vpr command line option
--astar_fac <float>
vpr command line option
--auto <int>
vpr command line option
--balance_block_type_utilization {on
vpr command line option
--base_cost_type {demand_only | delay_normalized | delay_normalized_length | delay_normalized_frequency | delay_normalized_length_frequency}
vpr command line option
--bb_factor <int>
vpr command line option
--bend_cost <float>
vpr command line option
--beta_clustering <float>
vpr command line option
--circuit_file <file>
vpr command line option
--circuit_format {auto | blif | eblif}
vpr command line option
--clock_modeling {ideal | route | dedicated_network}
vpr command line option
--cluster_seed_type {blend | timing | max_inputs}
vpr command line option
--clustering_pin_feasibility_filter {on | off}
vpr command line option
--congested_routing_iteration_threshold CONGESTED_ROUTING_ITERATION_THRESHOLD
vpr command line option
--connection_driven_clustering {on | off}
vpr command line option
--const_gen_inference {none | comb | comb_seq}
vpr command line option
--constant_net_method {global | route}
vpr command line option
--criticality_exp <float>
vpr command line option
--device <string>
vpr command line option
--disp {on | off}
vpr command line option
--echo_dot_timing_graph_node { string | int }
vpr command line option
--echo_file {on | off}
vpr command line option
--enable_timing_computations {on | off}
vpr command line option
--exit_before_pack {on | off}
vpr command line option
--exit_t <float>
vpr command line option
--first_iter_pres_fac <float>
vpr command line option
--fix_pins {free | random | <file.pads>}
vpr command line option
--full_stats
vpr command line option
--gen_post_synthesis_netlist { on | off }
vpr command line option
--graphics_commands <string>
vpr command line option
--help
vpr command line option
--incremental_reroute_delay_ripup {on | off | auto}
vpr command line option
--init_t <float>
vpr command line option
--initial_pres_fac <float>
vpr command line option
--inner_loop_recompute_divider <int>
vpr command line option
--inner_num <float>
vpr command line option
--max_criticality <float>
vpr command line option
--max_router_iterations <int>
vpr command line option
--min_incremental_reroute_fanout <int>
vpr command line option
--min_route_chan_width_hint <int>
vpr command line option
--net_file <file>
vpr command line option
--netlist_verbosity <int>
vpr command line option
--num_workers <int>
vpr command line option
--outfile_prefix <string>
vpr command line option
--pack
vpr command line option
--pack_feasible_block_array_size <int>
vpr command line option
--pack_high_fanout_threshold {auto | <int> | <string>:<int>}
vpr command line option
--pack_prioritize_transitive_connectivity {on | off}
vpr command line option
--pack_transitive_fanout_threshold <int>
vpr command line option
--pack_verbosity <int>
vpr command line option
--place
vpr command line option
--place_algorithm {bounding_box | path_timing_driven}
vpr command line option
--place_chan_width <int>
vpr command line option
--place_delay_model {delta
vpr command line option
--place_delay_model_reducer {min
vpr command line option
--place_delay_offset <float>
vpr command line option
--place_delay_ramp_delta_threshold <float>
vpr command line option
--place_delay_ramp_slope <float>
vpr command line option
--place_file <file>
vpr command line option
--place_rlim_escape <float>
vpr command line option
--place_tsu_abs_margin <float>
vpr command line option
--place_tsu_rel_margin <float>
vpr command line option
--post_place_timing_report <file>
vpr command line option
--power
vpr command line option
--pres_fac_mult <float>
vpr command line option
--read_rr_graph <file>
vpr command line option
--recompute_crit_iter <int>
vpr command line option
--route
vpr command line option
--route_bb_update {static
vpr command line option
--route_chan_width <int>
vpr command line option
--route_file <file>
vpr command line option
--route_type {global | detailed}
vpr command line option
--router_algorithm {breadth_first | timing_driven}
vpr command line option
--router_debug_net <int>
vpr command line option
--router_debug_sink_rr <int>
command line option
--router_debug_sink_rr ROUTER_DEBUG_SINK_RR
vpr command line option
--router_first_iter_timing_report <file>
vpr command line option
--router_high_fanout_threshold ROUTER_HIGH_FANOUT_THRESHOLD
vpr command line option
--router_init_wirelength_abort_threshold <float>
vpr command line option
--router_initial_timing {all_critical | lookahead}
vpr command line option
--router_lookahead {classic
vpr command line option
--router_max_convergence_count <float>
vpr command line option
--router_reconvergence_cpd_threshold <float>
vpr command line option
--router_update_lower_bound_delays {on | off}
vpr command line option
--routing_budgets_algorithm { disable | minimax | scale_delay }
vpr command line option
--routing_failure_predictor {safe | aggressive | off}
vpr command line option
--save_graphics {on | off}
vpr command line option
--save_routing_per_iteration {on | off}
vpr command line option
--sdc_file <file>
vpr command line option
--seed <int>
vpr command line option
--sink_rr_node <int>
command line option
--source_rr_node <int>
command line option
--strict_checks {on
vpr command line option
--sweep_constant_primary_outputs {on | off}
vpr command line option
--sweep_dangling_blocks {on | off}
vpr command line option
--sweep_dangling_nets {on | off}
vpr command line option
--sweep_dangling_primary_ios {on | off}
vpr command line option
--target_ext_pin_util { auto | <float> | <float>,<float> | <string>:<float> | <string>:<float>,<float> }
vpr command line option
--target_utilization <float>
vpr command line option
--td_place_exp_first <float>
vpr command line option
--td_place_exp_last <float>
vpr command line option
--tech_properties <file>
vpr command line option
--timing_analysis {on | off}
vpr command line option
--timing_driven_clustering {on|off}
vpr command line option
--timing_report_detail { netlist | aggregated | detailed }
vpr command line option
--timing_report_npaths <int>
vpr command line option
--timing_report_skew { on | off }
vpr command line option
--timing_tradeoff <float>
vpr command line option
--two_stage_clock_routing {on | off}
vpr command line option
--verify_binary_search {on | off}
vpr command line option
--verify_file_digests {on | off}
vpr command line option
--version
vpr command line option
--write_rr_graph <file>
vpr command line option
-adder_cin_global
run_vtr_flow.pl command line option
-check_golden
parse_vtr_task.pl command line option
-clock<virtualornetlistclock>
SDC Option
-cmos_tech <file>
run_vtr_flow.pl command line option
-create_golden
parse_vtr_task.pl command line option
-delete_intermediate_files
run_vtr_flow.pl command line option
-delete_result_files
run_vtr_flow.pl command line option
-early
SDC Option
-ending_stage <stage>
run_vtr_flow.pl command line option
-exclusive
SDC Option
-from[get_clocks<clocklistorregexes>]
SDC Option
,
[1]
,
[2]
,
[3]
-from[get_pins<pinlistorregexes>]
SDC Option
-group{<clocklistorregexes>}
SDC Option
-h
vpr command line option
-hold
SDC Option
,
[1]
-j
vpr command line option
-j <N>
run_vtr_task.pl command line option
-l <task_list_file>
parse_vtr_task.pl command line option
run_vtr_task.pl command line option
-late
SDC Option
-limit_memory_usage
run_vtr_flow.pl command line option
-max
SDC Option
-min
SDC Option
-min_hard_adder_size <int>
run_vtr_flow.pl command line option
-min_hard_mult_size <int>
run_vtr_flow.pl command line option
-name<string>
SDC Option
-period<float>
SDC Option
-power
run_vtr_flow.pl command line option
-s <script_param> ...
run_vtr_task.pl command line option
-setup
SDC Option
,
[1]
-source
SDC Option
-starting_stage <stage>
run_vtr_flow.pl command line option
-system {local | scripts}
run_vtr_task.pl command line option
-temp_dir <path>
run_vtr_flow.pl command line option
-timeout <float>
run_vtr_flow.pl command line option
-to[get_clocks<clocklistorregexes>]
SDC Option
,
[1]
,
[2]
,
[3]
-to[get_pins<pinlistorregexes>]
SDC Option
,
[1]
-track_memory_usage
run_vtr_flow.pl command line option
-valgrind
run_vtr_flow.pl command line option
-waveform{<float><float>}
SDC Option
<areagrid_logic_tile_area="float"/>
">Tag Attribute
<auto_layoutaspect_ratio="float">
">Tag Attribute
<block_typeid="int"name="unique_identifier"width="int"height="int">
">Tag Attribute
<bufferslogical_effort_factor="float"/>
">Tag Attribute
<cbtype="pattern">intlist</cb>
intlist">Tag Attribute
<chan_width_distr>content</chan_width_distr>
Tag Attribute
<channelchan_width_max="int"x_min="int"y_min="int"x_max="int"y_max="int"/>
">Tag Attribute
<clock_networkname="string"num_inst="integer">
">Tag Attribute
<clockC_wire="float"C_wire_per_m="float"buffer_size={"float"|"auto"}/>
">Tag Attribute
<clockname="string"num_pins="int"equivalent="{none|full}"/>
">Tag Attribute,
">[1]
<coltype="string"priority="int"startx="expr"repeatx="expr"starty="expr"incry="expr"/>
">Tag Attribute
<completename="string"input="string"output="string"/>
">Tag Attribute
<complexblocklist>content</complexblocklist>
Tag Attribute
<connection_blockinput_switch_name="string"/>
">Tag Attribute
<cornerstype="string"priority="int"/>
">Tag Attribute
<default_fcin_type="{frac|abs}"in_val="{int|float}"out_type="{frac|abs}"out_val="{int|float}"/>
">Tag Attribute
<delay>
SDC Option
,
[1]
<delay_constantmax="float"min="float"in_port="string"out_port="string"/>
">Tag Attribute
<delay_matrixtype="{max|min}"in_port="string"out_port="string">matrix</delay>
matrix">Tag Attribute
<device>content</device>
Tag Attribute
<directfrom="string"to="string">
">Tag Attribute
<directname="string"from_pin="string"to_pin="string"x_offset="int"y_offset="int"z_offset="int"switch_name="string"/>
">Tag Attribute
<directname="string"input="string"output="string"/>
">Tag Attribute
<dynamic_powerpower_per_instance="float"C_internal="float"/>
">Tag Attribute
<edgesrc_node="int"sink_node="int"switch_id="int"/>
">Tag Attribute
<equivalent_sites>
Tag Attribute
<fc_overridefc_type="{frac|abs}"fc_val="{int|float}",port_name="{string}"segment_name="{string}">
">Tag Attribute
<fcin_type="{frac|abs}"in_val="{int|float}"out_type="{frac|abs}"out_val="{int|float}">
">Tag Attribute
<filltype="string"priority="int"/>
">Tag Attribute
<fixed_layoutname="string"width="int"height="int">
">Tag Attribute
<fromtype="string"switchpoint="int,int,int,..."/>
">Tag Attribute
<functype="string"formula="string"/>
">Tag Attribute
<grid_locx="int"y="int"block_type_id="int"width_offset="int"height_offset="int">
">Tag Attribute
<inputname="string"num_pins="int"equivalent="{none|full}"is_non_clock_global="{true|false}"/>
">Tag Attribute,
">[1]
<latency>
SDC Option
<layout/>
Tag Attribute
<local_interconnectC_wire="float"factor="float"/>
">Tag Attribute
<locside="{left|right|bottom|top}"xoffset="int"yoffset="int">name_of_complex_logic_block.port_name[int:int]...</loc>
name_of_complex_logic_block.port_name[int:int]...">Tag Attribute
<locxlow="int"ylow="int"xhigh="int"yhigh="int"side="{LEFT|RIGHT|TOP|BOTTOM}"ptc="int">
">Tag Attribute
<metadata>
Tag Attribute
<metal_layername="string"Rmetal="float"Cmetal="float"/>
">Tag Attribute
<metaname="string">
">Tag Attribute
<modename="string">
">Tag Attribute
<muxname="string"/>
">Tag Attribute
<muxname="string"input="string"output="string"/>
">Tag Attribute
<netlistclocklistorregexes>
SDC Option
<nodeid="int"type="unique_type"direction="unique_direction"capacity="int">
">Tag Attribute
<opin_switchname="string"/>
">Tag Attribute
<outputname="string"num_pins="int"equivalent="{none|full|instance}"/>
">Tag Attribute,
">[1]
<pack_patternname="string"in_port="string"out_port="string"/>
">Tag Attribute
<path_multiplier>
SDC Option
<pb_typename="string"num_pb="int"blif_model="string"/>
">Tag Attribute
<perimetertype="string"priority="int"/>
">Tag Attribute
<pin_classtype="pin_type">
">Tag Attribute
<pinlocationspattern="{spread|perimeter|custom}">
">Tag Attribute
<pinptc="block_pin_index">name</pin>
name">Tag Attribute
<portname="string"energy_per_toggle="float"scaled_by_static_prob="string"scaled_by_static_prob_n="string"/>
">Tag Attribute
<portname="string"is_clock="{0|1}clock="string"combinational_sink_ports="string1string2..."/>
">Tag Attribute
<powermethod="string">contents</power>
contents">Tag Attribute
<regiontype="string"priority="int"startx="expr"endx="exprrepeatx="expr"incrx="expr"starty="expr"endy="expr"repeaty="expr"incry="expr"/>
">Tag Attribute
<ribmetal_layer="string"y="expr"startx="expr"endx="expr"repeatx="expr"repeaty="expr"/>
">Tag Attribute
<rowtype="string"priority="int"starty="expr"repeaty="expr"startx="expr"/>
">Tag Attribute
<sb_loctype="{full|straight|turns|none}"xoffset="int"yoffset="int",switch_override="string">
">Tag Attribute
<sbtype="pattern">intlist</sb>
intlist">Tag Attribute
<segmentid="int"name="unique_identifier">
">Tag Attribute
<segmentlist>content</segmentlist>
Tag Attribute
<segmentname="unique_name"length="int"type="{bidir|unidir}"freq="float"Rmetal="float"Cmetal="float">content</segment>
content">Tag Attribute
<segmentsegment_id="int">
">Tag Attribute
<singletype="string"priority="int"x="expr"y="expr"/>
">Tag Attribute
<sitepb_type="string"pin_mapping="string"/>
">Tag Attribute
<sizingmux_trans_size="int"buf_size="float"/>
">Tag Attribute
<sizingR_minW_nmos="float"R_minW_pmos="float"/>
">Tag Attribute
<spinemetal_layer="string"x="expr"starty="expr"endy="expr"repeatx="expr"repeaty="expr"/>
">Tag Attribute
<static_powerpower_per_instance="float"/>
">Tag Attribute
<sub_tilename"string"capacity="{int}">
">Tag Attribute
<switch_blocktype="{wilton|subset|universal|custom}"fs="int"/>
">Tag Attribute
<switch_pointtype="{drive|tap}"name="string"yoffset="expr"xoffset="expr"xinc="expr"yinc="expr"buffer="string">
">Tag Attribute
<switchblock_locationspattern="{external_full_internal_straight|all|external|internal|none|custom}"internal_switch="string">
">Tag Attribute
<switchblock_locationtype="string"/>
">Tag Attribute
<switchblockname="string"type="string">
">Tag Attribute
<switchfuncs>
Tag Attribute
<switchid="int"name="unique_identifier"type="{mux|tristate|pass_gate|short|buffer}">
">Tag Attribute
<switchlist>content</switchlist>
Tag Attribute
<switchtype="{mux|tristate|pass_gate|short|buffer}"name="string"R="float"Cin="float"Cout="float"Cinternal="float"Tdel="float"buf_size="{auto|float}"mux_trans_size="float",power_buf_size="int"/>
">Tag Attribute
<T_clock_to_Qmax="float"min="float"port="string"clock="string"/>
">Tag Attribute
<T_holdvalue="float"port="string"clock="string"/>
">Tag Attribute
<T_setupvalue="float"port="string"clock="string"/>
">Tag Attribute
<tapfrom="string"to="string"locationx="expr"locationy="expr"switch="string"fc_val="float">
">Tag Attribute
<Tdelnum_inputs="int"delay="float"/>
">Tag Attribute
<tilename="string"capacity="int"width="int"height="int"area="float"/>
">Tag Attribute
<tiles>content</tiles>
Tag Attribute
<timingR="float"C="float">
">Tag Attribute
<timingR="float"cin="float"Cout="float"Tdel="float/>
">Tag Attribute
<timingR_per_meter="float"C_per_meter="float">
">Tag Attribute
<totype="string"switchpoint="int,int,int,..."/>
">Tag Attribute
<uncertainty>
SDC Option
<wire_switchname="string"/>
">Tag Attribute
<wireconnnum_conns="expr"from_type="string,string,string,..."to_type="string,string,string,..."from_switchpoint="int,int,int,..."to_switchpoint="int,int,int,..."from_order="{fixed|shuffled}"to_order="{fixed|shuffled}"/>
">Tag Attribute
<x_listindex="int"info="int"/><y_listindex="int"info="int"/>
">Tag Attribute
<xdistr="{gaussian|uniform|pulse|delta}"peak="float"width="float"xpeak="float"dc="float"/>
">Tag Attribute
<ydistr="{gaussian|uniform|pulse|delta}"peak="float"width="float"xpeak="float"dc="float"/>
">Tag Attribute
[get_clocks<clocklistorregexes>]
SDC Option
[get_ports{<I/Olistorregexes>}]
SDC Option
A
Arc
architecture
vpr command line option
arithmean
vpr command line option
ASIC
,
[1]
auto}
vpr command line option
B
basic element
basic logic element
BEL
Bitstream
,
[1]
BLE
Block RAM
C
CFA
circuit
vpr command line option
class="flipflop"
Tag Attribute
class="lut"
Tag Attribute
class="memory"
Tag Attribute
CLB
Clock
Clock backbone
Clock domain
Clock region
Clock spine
Column
command line option
--router_debug_sink_rr <int>
--sink_rr_node <int>
--source_rr_node <int>
Configurable logic block
create_clock
SDC Command
D
Database
,
[1]
delta_override}
vpr command line option
dynamic}
vpr command line option
F
Fabric sub region
FF
,
[1]
Flip flop
,
[1]
FPGA
,
[1]
Frame
,
[1]
Frame base address
FSR
Fuzzer
,
[1]
G
General Routing
geomean}
vpr command line option
Global Routing
H
Half
,
[1]
HDL
,
[1]
Horizontal clock row
HROW
I
I/O block
INT
Interconnect tile
Internal Routing
L
LUT
,
[1]
M
map}
vpr command line option
max
vpr command line option
median
vpr command line option
MUX
,
[1]
MWTA
N
Node
,
[1]
O
off
vpr command line option
off}
vpr command line option
P
parse_vtr_task.pl command line option
-check_golden
-create_golden
-l <task_list_file>
PIP
Place and route
,
[1]
PnR
,
[1]
Programmable interconnect point
Q
Quadrant
R
Region of interest
ROI
Routing fabric
,
[1]
run_vtr_flow.pl command line option
-adder_cin_global
-cmos_tech <file>
-delete_intermediate_files
-delete_result_files
-ending_stage <stage>
-limit_memory_usage
-min_hard_adder_size <int>
-min_hard_mult_size <int>
-power
-starting_stage <stage>
-temp_dir <path>
-timeout <float>
-track_memory_usage
-valgrind
run_vtr_task.pl command line option
-j <N>
-l <task_list_file>
-s <script_param> ...
-system {local | scripts}
S
SDC Command
#(comment),\\(linecontinued),*(wildcard),{}(stringescape)
create_clock
set_clock_groups
set_clock_latency
set_clock_uncertainty
set_disable_timing
set_false_path
set_input_delay/set_output_delay
set_max_delay/set_min_delay
set_multicycle_path
SDC Option
-clock<virtualornetlistclock>
-early
-exclusive
-from[get_clocks<clocklistorregexes>]
,
[1]
,
[2]
,
[3]
-from[get_pins<pinlistorregexes>]
-group{<clocklistorregexes>}
-hold
,
[1]
-late
-max
-min
-name<string>
-period<float>
-setup
,
[1]
-source
-to[get_clocks<clocklistorregexes>]
,
[1]
,
[2]
,
[3]
-to[get_pins<pinlistorregexes>]
,
[1]
-waveform{<float><float>}
<delay>
,
[1]
<latency>
<netlistclocklistorregexes>
<path_multiplier>
<uncertainty>
[get_clocks<clocklistorregexes>]
[get_ports{<I/Olistorregexes>}]
Segment
set_clock_groups
SDC Command
set_clock_latency
SDC Command
set_clock_uncertainty
SDC Command
set_disable_timing
SDC Command
set_false_path
SDC Command
set_input_delay/set_output_delay
SDC Command
set_max_delay/set_min_delay
SDC Command
set_multicycle_path
SDC Command
Site
,
[1]
Slice
Specimen
,
[1]
T
Tag Attribute
"><areagrid_logic_tile_area="float"/>
"><auto_layoutaspect_ratio="float">
"><block_typeid="int"name="unique_identifier"width="int"height="int">
"><bufferslogical_effort_factor="float"/>
intlist"><cbtype="pattern">intlist</cb>
<chan_width_distr>content</chan_width_distr>
"><channelchan_width_max="int"x_min="int"y_min="int"x_max="int"y_max="int"/>
"><clock_networkname="string"num_inst="integer">
"><clockC_wire="float"C_wire_per_m="float"buffer_size={"float"|"auto"}/>
"><clockname="string"num_pins="int"equivalent="{none|full}"/>,
">[1]
"><coltype="string"priority="int"startx="expr"repeatx="expr"starty="expr"incry="expr"/>
"><completename="string"input="string"output="string"/>
<complexblocklist>content</complexblocklist>
"><connection_blockinput_switch_name="string"/>
"><cornerstype="string"priority="int"/>
"><default_fcin_type="{frac|abs}"in_val="{int|float}"out_type="{frac|abs}"out_val="{int|float}"/>
"><delay_constantmax="float"min="float"in_port="string"out_port="string"/>
matrix"><delay_matrixtype="{max|min}"in_port="string"out_port="string">matrix</delay>
<device>content</device>
"><directfrom="string"to="string">
"><directname="string"from_pin="string"to_pin="string"x_offset="int"y_offset="int"z_offset="int"switch_name="string"/>
"><directname="string"input="string"output="string"/>
"><dynamic_powerpower_per_instance="float"C_internal="float"/>
"><edgesrc_node="int"sink_node="int"switch_id="int"/>
<equivalent_sites>
"><fc_overridefc_type="{frac|abs}"fc_val="{int|float}",port_name="{string}"segment_name="{string}">
"><fcin_type="{frac|abs}"in_val="{int|float}"out_type="{frac|abs}"out_val="{int|float}">
"><filltype="string"priority="int"/>
"><fixed_layoutname="string"width="int"height="int">
"><fromtype="string"switchpoint="int,int,int,..."/>
"><functype="string"formula="string"/>
"><grid_locx="int"y="int"block_type_id="int"width_offset="int"height_offset="int">
"><inputname="string"num_pins="int"equivalent="{none|full}"is_non_clock_global="{true|false}"/>,
">[1]
<layout/>
"><local_interconnectC_wire="float"factor="float"/>
name_of_complex_logic_block.port_name[int:int]..."><locside="{left|right|bottom|top}"xoffset="int"yoffset="int">name_of_complex_logic_block.port_name[int:int]...</loc>
"><locxlow="int"ylow="int"xhigh="int"yhigh="int"side="{LEFT|RIGHT|TOP|BOTTOM}"ptc="int">
<metadata>
"><metal_layername="string"Rmetal="float"Cmetal="float"/>
"><metaname="string">
"><modename="string">
"><muxname="string"/>
"><muxname="string"input="string"output="string"/>
"><nodeid="int"type="unique_type"direction="unique_direction"capacity="int">
"><opin_switchname="string"/>
"><outputname="string"num_pins="int"equivalent="{none|full|instance}"/>,
">[1]
"><pack_patternname="string"in_port="string"out_port="string"/>
"><pb_typename="string"num_pb="int"blif_model="string"/>
"><perimetertype="string"priority="int"/>
"><pin_classtype="pin_type">
"><pinlocationspattern="{spread|perimeter|custom}">
name"><pinptc="block_pin_index">name</pin>
"><portname="string"energy_per_toggle="float"scaled_by_static_prob="string"scaled_by_static_prob_n="string"/>
"><portname="string"is_clock="{0|1}clock="string"combinational_sink_ports="string1string2..."/>
contents"><powermethod="string">contents</power>
"><regiontype="string"priority="int"startx="expr"endx="exprrepeatx="expr"incrx="expr"starty="expr"endy="expr"repeaty="expr"incry="expr"/>
"><ribmetal_layer="string"y="expr"startx="expr"endx="expr"repeatx="expr"repeaty="expr"/>
"><rowtype="string"priority="int"starty="expr"repeaty="expr"startx="expr"/>
"><sb_loctype="{full|straight|turns|none}"xoffset="int"yoffset="int",switch_override="string">
intlist"><sbtype="pattern">intlist</sb>
"><segmentid="int"name="unique_identifier">
<segmentlist>content</segmentlist>
content"><segmentname="unique_name"length="int"type="{bidir|unidir}"freq="float"Rmetal="float"Cmetal="float">content</segment>
"><segmentsegment_id="int">
"><singletype="string"priority="int"x="expr"y="expr"/>
"><sitepb_type="string"pin_mapping="string"/>
"><sizingmux_trans_size="int"buf_size="float"/>
"><sizingR_minW_nmos="float"R_minW_pmos="float"/>
"><spinemetal_layer="string"x="expr"starty="expr"endy="expr"repeatx="expr"repeaty="expr"/>
"><static_powerpower_per_instance="float"/>
"><sub_tilename"string"capacity="{int}">
"><switch_blocktype="{wilton|subset|universal|custom}"fs="int"/>
"><switch_pointtype="{drive|tap}"name="string"yoffset="expr"xoffset="expr"xinc="expr"yinc="expr"buffer="string">
"><switchblock_locationspattern="{external_full_internal_straight|all|external|internal|none|custom}"internal_switch="string">
"><switchblock_locationtype="string"/>
"><switchblockname="string"type="string">
<switchfuncs>
"><switchid="int"name="unique_identifier"type="{mux|tristate|pass_gate|short|buffer}">
<switchlist>content</switchlist>
"><switchtype="{mux|tristate|pass_gate|short|buffer}"name="string"R="float"Cin="float"Cout="float"Cinternal="float"Tdel="float"buf_size="{auto|float}"mux_trans_size="float",power_buf_size="int"/>
"><T_clock_to_Qmax="float"min="float"port="string"clock="string"/>
"><T_holdvalue="float"port="string"clock="string"/>
"><T_setupvalue="float"port="string"clock="string"/>
"><tapfrom="string"to="string"locationx="expr"locationy="expr"switch="string"fc_val="float">
"><Tdelnum_inputs="int"delay="float"/>
"><tilename="string"capacity="int"width="int"height="int"area="float"/>
<tiles>content</tiles>
"><timingR="float"C="float">
"><timingR="float"cin="float"Cout="float"Tdel="float/>
"><timingR_per_meter="float"C_per_meter="float">
"><totype="string"switchpoint="int,int,int,..."/>
"><wire_switchname="string"/>
"><wireconnnum_conns="expr"from_type="string,string,string,..."to_type="string,string,string,..."from_switchpoint="int,int,int,..."to_switchpoint="int,int,int,..."from_order="{fixed|shuffled}"to_order="{fixed|shuffled}"/>
"><x_listindex="int"info="int"/><y_listindex="int"info="int"/>
"><xdistr="{gaussian|uniform|pulse|delta}"peak="float"width="float"xpeak="float"dc="float"/>
"><ydistr="{gaussian|uniform|pulse|delta}"peak="float"width="float"xpeak="float"dc="float"/>
class="flipflop"
class="lut"
class="memory"
Tile
,
[1]
V
vpr command line option
--absorb_buffer_luts {on | off}
--acc_fac <float>
--activity_file <file>
--allow_unrelated_clustering {on | off | auto}
--alpha_clustering <float>
--alpha_t <float>
--analysis
--astar_fac <float>
--auto <int>
--balance_block_type_utilization {on
--base_cost_type {demand_only | delay_normalized | delay_normalized_length | delay_normalized_frequency | delay_normalized_length_frequency}
--bb_factor <int>
--bend_cost <float>
--beta_clustering <float>
--circuit_file <file>
--circuit_format {auto | blif | eblif}
--clock_modeling {ideal | route | dedicated_network}
--cluster_seed_type {blend | timing | max_inputs}
--clustering_pin_feasibility_filter {on | off}
--congested_routing_iteration_threshold CONGESTED_ROUTING_ITERATION_THRESHOLD
--connection_driven_clustering {on | off}
--const_gen_inference {none | comb | comb_seq}
--constant_net_method {global | route}
--criticality_exp <float>
--device <string>
--disp {on | off}
--echo_dot_timing_graph_node { string | int }
--echo_file {on | off}
--enable_timing_computations {on | off}
--exit_before_pack {on | off}
--exit_t <float>
--first_iter_pres_fac <float>
--fix_pins {free | random | <file.pads>}
--full_stats
--gen_post_synthesis_netlist { on | off }
--graphics_commands <string>
--help
--incremental_reroute_delay_ripup {on | off | auto}
--init_t <float>
--initial_pres_fac <float>
--inner_loop_recompute_divider <int>
--inner_num <float>
--max_criticality <float>
--max_router_iterations <int>
--min_incremental_reroute_fanout <int>
--min_route_chan_width_hint <int>
--net_file <file>
--netlist_verbosity <int>
--num_workers <int>
--outfile_prefix <string>
--pack
--pack_feasible_block_array_size <int>
--pack_high_fanout_threshold {auto | <int> | <string>:<int>}
--pack_prioritize_transitive_connectivity {on | off}
--pack_transitive_fanout_threshold <int>
--pack_verbosity <int>
--place
--place_algorithm {bounding_box | path_timing_driven}
--place_chan_width <int>
--place_delay_model {delta
--place_delay_model_reducer {min
--place_delay_offset <float>
--place_delay_ramp_delta_threshold <float>
--place_delay_ramp_slope <float>
--place_file <file>
--place_rlim_escape <float>
--place_tsu_abs_margin <float>
--place_tsu_rel_margin <float>
--post_place_timing_report <file>
--power
--pres_fac_mult <float>
--read_rr_graph <file>
--recompute_crit_iter <int>
--route
--route_bb_update {static
--route_chan_width <int>
--route_file <file>
--route_type {global | detailed}
--router_algorithm {breadth_first | timing_driven}
--router_debug_net <int>
--router_debug_sink_rr ROUTER_DEBUG_SINK_RR
--router_first_iter_timing_report <file>
--router_high_fanout_threshold ROUTER_HIGH_FANOUT_THRESHOLD
--router_init_wirelength_abort_threshold <float>
--router_initial_timing {all_critical | lookahead}
--router_lookahead {classic
--router_max_convergence_count <float>
--router_reconvergence_cpd_threshold <float>
--router_update_lower_bound_delays {on | off}
--routing_budgets_algorithm { disable | minimax | scale_delay }
--routing_failure_predictor {safe | aggressive | off}
--save_graphics {on | off}
--save_routing_per_iteration {on | off}
--sdc_file <file>
--seed <int>
--strict_checks {on
--sweep_constant_primary_outputs {on | off}
--sweep_dangling_blocks {on | off}
--sweep_dangling_nets {on | off}
--sweep_dangling_primary_ios {on | off}
--target_ext_pin_util { auto | <float> | <float>,<float> | <string>:<float> | <string>:<float>,<float> }
--target_utilization <float>
--td_place_exp_first <float>
--td_place_exp_last <float>
--tech_properties <file>
--timing_analysis {on | off}
--timing_driven_clustering {on|off}
--timing_report_detail { netlist | aggregated | detailed }
--timing_report_npaths <int>
--timing_report_skew { on | off }
--timing_tradeoff <float>
--two_stage_clock_routing {on | off}
--verify_binary_search {on | off}
--verify_file_digests {on | off}
--version
--write_rr_graph <file>
-h
-j
architecture
arithmean
auto}
circuit
delta_override}
dynamic}
geomean}
map}
max
median
off
off}
W
Wire
,
[1]
Word